
7-5
Publication 1771Ć6.5.116 - May 1996
Figure 7.3
Block Transfer Read in Two's Complement - Data First Configuration, Differential
Inputs
Dec. Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Octal Bits 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00
Word 1 Channel 1 Input Channel 1 Input
2 Channel 2 Input Channel 2 Input
3 Channel 3 Input Channel 3 Input
4 Channel 4 Input Channel 4 Input
5 Channel 5 Input Channel 16 Input
6 Channel 6 Input Channel 1 Input
7 Channel 7 Input Channel 2 Input
8 Channel 8 Input Channel 3 Input
9 HF EE CS RTS IS OR PU Diagnostics
10 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data underrange for channels 1-16
1
11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data overrange for channels 1-16
1
12 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data polarity for channels 1-16
13 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Offset Calibration Results
14 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Gain Calibration Results
15 15Ćbit rolling counter - binary, 1ms resolution Time Stamp
16 Update rate - binary, to 1υs, with +4µs resolution Scan Time
17-24 Not used (0)
Where: PU = Power up bit
OR = Out of range bit
IS = Invalid scaling bit
RTS = Real time sampling bit
HF = Hardware Fault
EE = EEPROM status bits
CS = Calibration status bits
1
These bits are set (1) at approximately the input range limits selected (Table NO TAG).
In this chapter you learned the meaning of the status information that
the input module sends to the processor.
Chapter Summary
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