
BĆ1
Appendix B
Module Block Diagram
Common Memory Module (57C413 and 57C423)
ADDRESS
ID BUS
BUS
BUS
BUS
ADDRESS
CONTROL
LOGIC
INITIALIZE
BYTE HI EN
WRITE MEM
READ MEM
YACK
ADDRESS
DECODER
WDOG OK
BD RESET
EVEN
SLOT
READ
WRITE
SYSTEM WATCHDOG INTERRUPT
BATTERY
BACKUP
DATA
TRANSCEIVERS
SYSTEM
WATCHDOG
BUS
ARBITRATION
BUSY
BUS GRANTS
BCLK
BUS REQUESTS
RAM
MEMORY
64K x 16 = M/N 57C413B
128K x 16 = M/N 57C423
SLOT 0
BUS CLOCK OK
DIAGNOSTICS OK
BAT. OK
SYSTEM
WATCHDOG
Common Memory Module (57C413)
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