Rockwell-automation 1761 MicroLogix 1000 Programmable Controllers Manual de usuario descargar pdf (Pagina 298)

100

101

Preface

MicroLogix 1000 Programmable Controllers User Manual

B–10

Address Bit Classification Description

S:2/14 Math Overflow

Selection

Dynamic

Configuration

Set this bit when you intend to use 32-bit

addition and subtraction. When S:2/14 is set,

and the result of an ADD, SUB, MUL, or DIV

instruction cannot be represented in the

destination address (underflow or overflow),

• the overflow bit S:0/1 is set,

• the overflow trap bit S:5/0 is set,

• and the destination address contains the

unsigned truncated least significant 16 bits

of the result.

The default condition of S:2/14 is reset (0).

When S:2/14 is reset, and the result of an

ADD, SUB, MUL, or DIV instruction cannot be

represented in the destination address

(underflow or overflow),

• the overflow bit S:0/1 is set,

• the overflow trap bit S:5/0 is set,

• and the destination address contains

32767 if the result is positive or – 32768 if

the result is negative.

Note, the status of bit S:2/14 has no effect on

the DDV instruction. Also, it has no effect on

the math register content when using MUL and

DIV instructions.

To provide protection from inadvertent

alteration of your selection, program an

unconditional OTL instruction at address

S:2/14 to ensure the new math overflow

operation. Program an unconditional OTU

instruction at address S:2/14 to ensure the

original math overflow operation.

S:2/15 Reserved NA NA

1 2 ... 293 294 295 296 297 298 299 300 301 302 303 ... 421 422

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