
Full-Duplex Protocol
Chapter 10
1022
If you were to connect a line monitor to the wires between station A and
B, and only the A to B subsystem were active, you could observe the
following:
Examples
Normal Message
Path 1: DLE STX xxxDLE ETX BCC DLE STXxxxxDLE ETX BCC
Path 2: DLE ACK DLE ACK
Message with parity or BCC error and recovery
Path 1: DLE STXxx???xxDLE ETX BCC DLE STXxxxxDLE ETX BCC
Path 2: DLE NAK DLE ACK
Message with ETX destroyed
Path 1: DLE STXxxxxx????[timeout] DLE ENQ DLE STXxxxxDLE ETX BCC
Path 2: DLE NAK DLE ACK
Good message but ACK destroyed
Path 1: DLE STXxxxDLE ETX BCC [timeout] DLE ENQ DLE STXxxx etc.
Path 2: DL???CK DLE ACK
Messages being sent in both directions
Path 1: DLE STXxxxDLE ETX BCC DLE STXxxxxDLE ETX BCC DLE STX
Path 2: DLE ACK DLE ACK
Path 3: DLE STXxxx xxxxDLE ETX BCC DLE STX
Path 4: DLE ACK
Combined –
Circuit AB:DLE STXxxxDLE ETX BCC DLE STXxxxxDLE ETX BCC DLE ACK DLE STX
Circuit BA: DLE STXxxxDLE ACKxxxxDLE ETX BCC DLE ACK DLE STX
embedded response
ACK on AB delayed slightly because ETX BCC are indivisible
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