
APPENDIX D
49’1340 e FlexPak 3000 D-9
From Speed Ref Source
Select Block Diagram
From Speed Loop
Block Diagram
(TORQUE REFERENCE)
(SPD LOOP OUTPUT)
MAXIMUM CURRENT
NORMALIZED INERTIA
Software
Scaling
S-curve rate output from
Speed Reference Ramp
Block Diagram
From I/O Expansion
Inputs Block Diagram
From Network
0
*NONE
INTERNAL
ANALOG IN 1
ANALOG IN 2
NETW IN REG 1, 2, 3
INERTIA
COMP
SELECT
Negative current limit from
Speed Loop Block Diagram
*SPEED/VOLTAGE
+
+
CURRENT/TORQUE
J15
REGULATOR
TYPE
Positive current limit from
Speed Loop Block Diagram
* = Default Selection
{
RATELIM
ACC/DEC
CML REF RATE LIMIT
(CML REFERENCE)
To Current
Minor Loop
Block Diagram
D.10(C)
HI
LO
LIMIT
P.303
P.396
P.005
P.189
P.299
P.221
P.222P.007
D3(A)
D5(A)
D6(A)
D13
D.6(C)
P.814
OCL Type3
POS REG EN 3)
(A)
(B)
UNDERWIND ENABLE 1)
Drop 1, Reg 32, Bit 5
EN
NEG CURRENT LIM INV EN 2)
P
.
2
2
6
POS CURRENT LIM
* SPD LOOP CUR LIM
REGISTER
CML REF LIMIT SELECT
P
.
3
1
1
EN
* SPD LOOP CUR LIM
REGISTER
CML REF LIMIT SELECT
P
.
3
1
1
NOTE 1) Network only register. CSS must be set to NETWORK
and NETW REGISTER MAP SEL = ALTERNATE
NOTE 2) Also enables/disables on inverter speed loop block diagram.
Forward/Reverse
Command
EN
From OCL
Block Diagram
P.848 (OCL Output)
ENABLED
*DISABLED
NOTE 3) Can only be set to enable when J15 REGULATOE TYPE
is set to CURRENT/TORQUE
D12(A)
Figure D.9 - Current Minor Loop Reference
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