Rockwell-automation 21G PowerFlex 750-Series AC Drives Programming Man Manual de usuario descargar pdf (Pagina 279)

Rockwell Automation Publication 750-PM001J-EN-P - October 2014 279

Embedded Feature and Option Module Parameters Chapter 5

Universal Feedback

Feedback 0

16 FB0 Inc Cfg

Feedback 0 Incremental Configuration

RW 16-bit

Integer

Configures Incremental Feedback for the feedback 0 device.

Bit 0 “Z Chan Enbl” – When set, Channel Z is also monitored for Phase Loss. When cleared, Channel Z is ignored for Phase Loss detection.

Only used if [FB0 Device Sel] = “Inc A B Z.”

Bit 1 “A Chan Only” – When set, logic monitors only channel A. When clear, logic monitors both A and B.

Bit 2 “Edge Mode” – When set, speed calc uses AB edge data. When clear, speed calc does not use AB edge data.

Bit 4 “Single Ended” – This bit has to be set if the connected A Quad B encoder has single ended signals. For these encoders, the Phase Loss detection is switched off.

17 FB0 Inc Sts

Feedback 0 Incremental Status

RO 16-bit

Integer

Displays Incremental Feedback status for the feedback 0 device.

Bit 0 “Z Chan Enbl” – Indicates that Channel Z is monitored for Phase Loss. Only used if [FB0 Device Sel] = “Inc A B Z.”

Bit 1 “A Chan Only” – Indicates only A channel is monitored, B channel not used.

Bit 2 “A Input” – State of encoder A input signal

Bit 3 “A Not Input” – State of encoder A Not input signal

Bit 4 “B Input” – State of encoder B input signal

Bit 5 “B Not Input” – State of encoder B Not input signal

Bit 6 “Z Input” – State of encoder Z input signal

Bit 7 “Z Not Input” – State of encoder Z Not input signal

20 FB0 SSI Cfg

Feedback 0 SSI Configuration

RW 16-bit

Integer

Configures the communication to a SSI encoder for the feedback 0 device. Transmission format: [MSB...Position...LSB], [Error Bit]*, [Parity Bit]*.

Bit 0 “Parity Bit” – If set, SSI encoder has to support a parity bit (even parity).

Bit 2 “Gray Code” – Enables the gray to binary conversion of the position.

Bit 3 “Err Bit Enbl” – If set, there is an error bit transmitted by the encoder.

Bit 4 “DblWordQuery” – If set, a Double Word Query is executed at startup which means that the same position is transmitted twice by the encoder. If the two

positions are not identical, the “Comm” error bit in [FB0 Sts] is set. This bit only needs to be cleared if the encoder does not support Double Word Query and it does

not send zeros instead of the second position (which it actually should according to the SSI specification).

File

Group

No. Display Name

Full Name

Description

Values

Read-Write

Data Type

Options

Reserved

Single Ended

Reserved

Edge Mode

A Chan Only

Z Chan Enbl

Default0000000000000100

Bit 1514131211109876543210

0 = Condition False

1 = Condition True

Options

Reserved

Z Not Input

Z Input

B Not Input

B Input

A Not Input

A Input

A Chan Only

Z Chan Enbl

Default0000000000000000

Bit 1514131211109876543210

0 = Condition False

1 = Condition True

Options

Reserved

DblWordQuery

Err Bit Enbl

Gray Code

Reserved

Parity Bit

Default0000000000010100

Bit 1514131211109876543210

0 = Condition False

1 = Condition True

1 2 ... 274 275 276 277 278 279 280 281 282 283 284 ... 543 544

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Rockwell-automation 21G PowerFlex 750-Series AC Drives Programming Man Manual de usuario Pagina 279

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