
374 Rockwell Automation Publication 750-PM001J-EN-P - October 2014
Appendix A PowerFlex 753 Control Block Diagrams
Figure 10 - Speed Control - Regulator (FV)
Speed Reg BW
Spd Loop Damping
Total Inertia
636
653
76
set param 636/648 = 0
to manually adjust
param 645/649 & 647/650
*
638
639
643
655
656
659
658
620
Droop
597
640
131
641
654
660
P Gain
kp
Limit
652
685
Spd Reg Pos Lmt
Spd Reg Neg Lmt
FeedFwd
nff
SReg FB FltrGain
SReg FB Fltr BW
Filtered SpdFdbk
Active Vel Fdbk
Final Speed Ref
Speed Error
SpdReg
AntiBckup
PTP PsnRefStatus
( PTP Int Hold)
Spd Options Ctrl
(SpdRegIntRes)
(SpdRegIntHld)
(Jog No Integ)
Selected Trq Ref
Droop RPM
at FLA
SReg Out
FltrGain
SReg Out
FltrBW
SReg Output
To Torq Ctrl
[17B2]
Spd Reg
Int Out
1
2
3
4
5
6
BA
D
C
FE HG
I
From
Fdbk
[3F2]
Lead Lag
(kn * s)+ wn
s + wn
Lead Lag
(kn * s)+ wn
s + wn
+
-
-
+
+
+
+
-
2
635
3
4
I Gain
ki
s
945
At Limit Status
Preset
Bumpless
Hold / Reset
Actv SpTqPs Mode
637SReg FB Fltr Sel
657
SReg OutFltr Sel
SReg Trq Preset
644Spd Err Filt BW*
2
nd
Order
LPass
Filter
635
Spd Options Cntl
(SpdErrFilter)
05
Alt Speed Reg BW
648
Set=1 Stage,
Clear=2 Stage
651
AltSpdErr FltrBW*
645Speed Reg Kp*
649Alt Speed Reg Kp*
945 4
At Limit Status
(Spd Reg Lmt)
720
647Speed Reg Ki*
650Alt Speed Reg Ki*
6
Speed Control – Regulator
Flux Vector
313
From
Spd
Ref
[9C2]
[17E2]
[17D5]
PF753 Rev_10.a
Page 10
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